In a prior art audio video reproduction apparatus, reproduction is performed by a method described below in which synchronization between video and audio is maintained (for example, see JP-A2001-8170). Further, FIG. 11 is a block diagram of a prior art audio video reproduction apparatus in which synchronization between video and audio is maintained even when reproduction is performed at a speed other than the single speed.
Here, the entire disclosure of JP-A2001-8170 is incorporated herein by reference in its entirety.
A system analyzing circuit 1 is a circuit of classifying input data into video data and audio data.
A video input buffer circuit 2 is a circuit of accumulating the video data outputted from the system analyzing circuit 1, while a video decoding circuit 3 is a circuit of acquiring the video data from the video input buffer circuit 2 and thereby decoding and converting the data into a video signal.
A video output buffer circuit 4 is a circuit of accumulating and outputting the video signal outputted from the video decoding circuit 3.
An audio input buffer circuit 5 is a circuit of accumulating the audio data outputted from the system analyzing circuit 1, while an audio decoding circuit 6 is a circuit of acquiring the audio data from the audio input buffer circuit 5 and thereby decoding and converting the data into an audio signal.
An audio output buffer circuit 9 is a circuit of accumulating and outputting the audio signal outputted from the audio decoding circuit 6.
A speed setting circuit 7 is a circuit of setting a desired speed in response to a user's instruction through a remote controller or the like. A video output control circuit 21 is a circuit which depending on the speed set by the speed setting circuit 7, outputs a control signal to the video output buffer circuit 4 so that the video signal is skipped when the continuation time is to be reduced, and which outputs a control signal to the video output buffer circuit 4 so that the video signal is frozen when the continuation time is to be extended.
An audio output control circuit 22 is a circuit which monitors the situation of accumulation of the audio signal in the audio output buffer circuit 9, and (1) which outputs a control signal to the audio output buffer circuit 9 so that the audio signal is skipped when the continuation time is to be reduced and hence when the audio signal tends to overflow in the audio output buffer circuit 9, and (2) which outputs a control signal to the audio output buffer circuit 9 so that the audio signal is repeated or paused when the continuation time is to be extended and hence when the audio signal tends to lack in the audio output buffer circuit 9.
Described next is the operation of the prior art audio video reproduction apparatus.
The system analyzing circuit 1 classifies input data into video data and audio data.
The video input buffer circuit 2 accumulates the video data outputted from the system analyzing circuit 1, while the video decoding circuit 3 acquires the video data from the video input buffer circuit 2 and thereby decodes and converts the data into a video signal.
The video output buffer circuit 4 accumulates and outputs the video signal outputted from the video decoding circuit 3.
The audio input buffer circuit 5 accumulates the audio data outputted from the system analyzing circuit 1, while the audio decoding circuit 6 acquires the audio data from the audio input buffer circuit 5 and thereby decodes and converts the data into an audio signal.
The audio output buffer circuit 9 accumulates and outputs the audio signal outputted from the audio decoding circuit 6.
The speed setting circuit 7 sets a desired speed in response to a user's instruction through a remote controller or the like. Depending on the speed set by the speed setting circuit 7, the video output control circuit 21 outputs a control signal to the video output buffer circuit 4 so that the video signal is skipped when the continuation time is to be reduced, and outputs a control signal to the video output buffer circuit 4 so that the video signal is frozen when the continuation time is to be extended.
The audio output control circuit 22 monitors the situation of accumulation of the audio signal in the audio output buffer circuit 9, and (1) outputs a control signal to the audio output buffer circuit 9 so that the audio signal is skipped when the continuation time is to be reduced and hence when the audio signal tends to overflow in the audio output buffer circuit 9, and (2) outputs a control signal to the audio output buffer circuit 9 so that the audio signal is repeated or paused when the continuation time is to be extended and hence when the audio signal tends to lack in the audio output buffer circuit 9.
Thus, (1) when the continuation time is to be reduced, a control signal is outputted to the audio output buffer circuit 9 so that the audio signal is skipped, whereby it is suppressed that the audio signal tends to overflow in the audio output buffer circuit 9, and (2) when the continuation time is to be extended, a control signal is outputted to the audio output buffer circuit 9 so that the audio signal is repeated or paused, whereby it is suppressed that the audio signal tends to lack in the audio output buffer circuit 9.
Nevertheless, in the prior art audio video reproduction apparatus described above, there has been the problem that during the changing of the speed such that the continuation time is reduced or extended, the output timing of the video signal and the output timing of the audio signal can largely deviate from each other in comparison with the case of normal reproduction, and that the synchronization can not be maintained.
Further, there are needs for fast browsing and slow listening. In such fast browsing and slow listening, the AV synchronization needs to be ensured.